i386-asm.c 50 KB

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  1. /*
  2. * i386 specific functions for TCC assembler
  3. *
  4. * Copyright (c) 2001, 2002 Fabrice Bellard
  5. * Copyright (c) 2009 Frédéric Feret (x86_64 support)
  6. *
  7. * This library is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU Lesser General Public
  9. * License as published by the Free Software Foundation; either
  10. * version 2 of the License, or (at your option) any later version.
  11. *
  12. * This library is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * Lesser General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU Lesser General Public
  18. * License along with this library; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include "tcc.h"
  22. #define MAX_OPERANDS 3
  23. #define TOK_ASM_first TOK_ASM_clc
  24. #define TOK_ASM_last TOK_ASM_emms
  25. #define TOK_ASM_alllast TOK_ASM_subps
  26. #define OPC_B 0x01 /* only used with OPC_WL */
  27. #define OPC_WL 0x02 /* accepts w, l or no suffix */
  28. #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
  29. #define OPC_REG 0x04 /* register is added to opcode */
  30. #define OPC_MODRM 0x08 /* modrm encoding */
  31. #define OPCT_MASK 0x70
  32. #define OPC_FWAIT 0x10 /* add fwait opcode */
  33. #define OPC_SHIFT 0x20 /* shift opcodes */
  34. #define OPC_ARITH 0x30 /* arithmetic opcodes */
  35. #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
  36. #define OPC_TEST 0x50 /* test opcodes */
  37. #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
  38. #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
  39. #define OPC_48 0x200 /* Always has REX prefix */
  40. #ifdef TCC_TARGET_X86_64
  41. # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
  42. # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
  43. # define OPC_WLX OPC_WLQ
  44. # define OPC_BWLX OPC_BWLQ
  45. #else
  46. # define OPC_WLX OPC_WL
  47. # define OPC_BWLX OPC_BWL
  48. #endif
  49. #define OPC_GROUP_SHIFT 13
  50. /* in order to compress the operand type, we use specific operands and
  51. we or only with EA */
  52. enum {
  53. OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
  54. OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
  55. OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
  56. #ifdef TCC_TARGET_X86_64
  57. OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
  58. #endif
  59. OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
  60. OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
  61. OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
  62. OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
  63. OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
  64. OPT_SEG,
  65. OPT_ST,
  66. #ifdef TCC_TARGET_X86_64
  67. OPT_REG8_LOW, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but
  68. with REX prefix, not used in insn templates */
  69. #endif
  70. OPT_IM8,
  71. OPT_IM8S,
  72. OPT_IM16,
  73. OPT_IM32,
  74. #ifdef TCC_TARGET_X86_64
  75. OPT_IM64,
  76. #endif
  77. OPT_EAX, /* %al, %ax, %eax or %rax register */
  78. OPT_ST0, /* %st(0) register */
  79. OPT_CL, /* %cl register */
  80. OPT_DX, /* %dx register */
  81. OPT_ADDR, /* OP_EA with only offset */
  82. OPT_INDIR, /* *(expr) */
  83. /* composite types */
  84. OPT_COMPOSITE_FIRST,
  85. OPT_IM, /* IM8 | IM16 | IM32 */
  86. OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
  87. OPT_REGW, /* REG16 | REG32 | REG64 */
  88. OPT_IMW, /* IM16 | IM32 */
  89. OPT_MMXSSE, /* MMX | SSE */
  90. OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
  91. OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */
  92. /* can be ored with any OPT_xxx */
  93. OPT_EA = 0x80
  94. };
  95. #define OP_REG8 (1 << OPT_REG8)
  96. #define OP_REG16 (1 << OPT_REG16)
  97. #define OP_REG32 (1 << OPT_REG32)
  98. #define OP_MMX (1 << OPT_MMX)
  99. #define OP_SSE (1 << OPT_SSE)
  100. #define OP_CR (1 << OPT_CR)
  101. #define OP_TR (1 << OPT_TR)
  102. #define OP_DB (1 << OPT_DB)
  103. #define OP_SEG (1 << OPT_SEG)
  104. #define OP_ST (1 << OPT_ST)
  105. #define OP_IM8 (1 << OPT_IM8)
  106. #define OP_IM8S (1 << OPT_IM8S)
  107. #define OP_IM16 (1 << OPT_IM16)
  108. #define OP_IM32 (1 << OPT_IM32)
  109. #define OP_EAX (1 << OPT_EAX)
  110. #define OP_ST0 (1 << OPT_ST0)
  111. #define OP_CL (1 << OPT_CL)
  112. #define OP_DX (1 << OPT_DX)
  113. #define OP_ADDR (1 << OPT_ADDR)
  114. #define OP_INDIR (1 << OPT_INDIR)
  115. #ifdef TCC_TARGET_X86_64
  116. # define OP_REG64 (1 << OPT_REG64)
  117. # define OP_REG8_LOW (1 << OPT_REG8_LOW)
  118. # define OP_IM64 (1 << OPT_IM64)
  119. # define OP_EA32 (OP_EA << 1)
  120. #else
  121. # define OP_REG64 0
  122. # define OP_REG8_LOW 0
  123. # define OP_IM64 0
  124. # define OP_EA32 0
  125. #endif
  126. #define OP_EA 0x40000000
  127. #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
  128. #ifdef TCC_TARGET_X86_64
  129. # define TREG_XAX TREG_RAX
  130. # define TREG_XCX TREG_RCX
  131. # define TREG_XDX TREG_RDX
  132. #else
  133. # define TREG_XAX TREG_EAX
  134. # define TREG_XCX TREG_ECX
  135. # define TREG_XDX TREG_EDX
  136. #endif
  137. typedef struct ASMInstr {
  138. uint16_t sym;
  139. uint16_t opcode;
  140. uint16_t instr_type;
  141. uint8_t nb_ops;
  142. uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
  143. } ASMInstr;
  144. typedef struct Operand {
  145. uint32_t type;
  146. int8_t reg; /* register, -1 if none */
  147. int8_t reg2; /* second register, -1 if none */
  148. uint8_t shift;
  149. ExprValue e;
  150. } Operand;
  151. static const uint8_t reg_to_size[9] = {
  152. /*
  153. [OP_REG8] = 0,
  154. [OP_REG16] = 1,
  155. [OP_REG32] = 2,
  156. #ifdef TCC_TARGET_X86_64
  157. [OP_REG64] = 3,
  158. #endif
  159. */
  160. 0, 0, 1, 0, 2, 0, 0, 0, 3
  161. };
  162. #define NB_TEST_OPCODES 30
  163. static const uint8_t test_bits[NB_TEST_OPCODES] = {
  164. 0x00, /* o */
  165. 0x01, /* no */
  166. 0x02, /* b */
  167. 0x02, /* c */
  168. 0x02, /* nae */
  169. 0x03, /* nb */
  170. 0x03, /* nc */
  171. 0x03, /* ae */
  172. 0x04, /* e */
  173. 0x04, /* z */
  174. 0x05, /* ne */
  175. 0x05, /* nz */
  176. 0x06, /* be */
  177. 0x06, /* na */
  178. 0x07, /* nbe */
  179. 0x07, /* a */
  180. 0x08, /* s */
  181. 0x09, /* ns */
  182. 0x0a, /* p */
  183. 0x0a, /* pe */
  184. 0x0b, /* np */
  185. 0x0b, /* po */
  186. 0x0c, /* l */
  187. 0x0c, /* nge */
  188. 0x0d, /* nl */
  189. 0x0d, /* ge */
  190. 0x0e, /* le */
  191. 0x0e, /* ng */
  192. 0x0f, /* nle */
  193. 0x0f, /* g */
  194. };
  195. static const uint8_t segment_prefixes[] = {
  196. 0x26, /* es */
  197. 0x2e, /* cs */
  198. 0x36, /* ss */
  199. 0x3e, /* ds */
  200. 0x64, /* fs */
  201. 0x65 /* gs */
  202. };
  203. static const ASMInstr asm_instrs[] = {
  204. #define ALT(x) x
  205. /* This removes a 0x0f in the second byte */
  206. #define O(o) ((uint64_t) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o)))
  207. /* This constructs instr_type from opcode, type and group. */
  208. #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
  209. #define DEF_ASM_OP0(name, opcode)
  210. #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0, { 0 } },
  211. #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
  212. #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
  213. #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
  214. #ifdef TCC_TARGET_X86_64
  215. # include "x86_64-asm.h"
  216. #else
  217. # include "i386-asm.h"
  218. #endif
  219. /* last operation */
  220. { 0, },
  221. };
  222. static const uint16_t op0_codes[] = {
  223. #define ALT(x)
  224. #define DEF_ASM_OP0(x, opcode) opcode,
  225. #define DEF_ASM_OP0L(name, opcode, group, instr_type)
  226. #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
  227. #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
  228. #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
  229. #ifdef TCC_TARGET_X86_64
  230. # include "x86_64-asm.h"
  231. #else
  232. # include "i386-asm.h"
  233. #endif
  234. };
  235. static inline int get_reg_shift(TCCState *s1)
  236. {
  237. int shift, v;
  238. v = asm_int_expr(s1);
  239. switch(v) {
  240. case 1:
  241. shift = 0;
  242. break;
  243. case 2:
  244. shift = 1;
  245. break;
  246. case 4:
  247. shift = 2;
  248. break;
  249. case 8:
  250. shift = 3;
  251. break;
  252. default:
  253. expect("1, 2, 4 or 8 constant");
  254. shift = 0;
  255. break;
  256. }
  257. return shift;
  258. }
  259. #ifdef TCC_TARGET_X86_64
  260. static int asm_parse_numeric_reg(int t, unsigned int *type)
  261. {
  262. int reg = -1;
  263. if (t >= TOK_IDENT && t < tok_ident) {
  264. const char *s = table_ident[t - TOK_IDENT]->str;
  265. char c;
  266. *type = OP_REG64;
  267. if (*s == 'c') {
  268. s++;
  269. *type = OP_CR;
  270. }
  271. if (*s++ != 'r')
  272. return -1;
  273. /* Don't allow leading '0'. */
  274. if ((c = *s++) >= '1' && c <= '9')
  275. reg = c - '0';
  276. else
  277. return -1;
  278. if ((c = *s) >= '0' && c <= '5')
  279. s++, reg = reg * 10 + c - '0';
  280. if (reg > 15)
  281. return -1;
  282. if ((c = *s) == 0)
  283. ;
  284. else if (*type != OP_REG64)
  285. return -1;
  286. else if (c == 'b' && !s[1])
  287. *type = OP_REG8;
  288. else if (c == 'w' && !s[1])
  289. *type = OP_REG16;
  290. else if (c == 'd' && !s[1])
  291. *type = OP_REG32;
  292. else
  293. return -1;
  294. }
  295. return reg;
  296. }
  297. #endif
  298. static int asm_parse_reg(unsigned int *type)
  299. {
  300. int reg = 0;
  301. *type = 0;
  302. if (tok != '%')
  303. goto error_32;
  304. next();
  305. if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
  306. reg = tok - TOK_ASM_eax;
  307. *type = OP_REG32;
  308. #ifdef TCC_TARGET_X86_64
  309. } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
  310. reg = tok - TOK_ASM_rax;
  311. *type = OP_REG64;
  312. } else if (tok == TOK_ASM_rip) {
  313. reg = -2; /* Probably should use different escape code. */
  314. *type = OP_REG64;
  315. } else if ((reg = asm_parse_numeric_reg(tok, type)) >= 0
  316. && (*type == OP_REG32 || *type == OP_REG64)) {
  317. ;
  318. #endif
  319. } else {
  320. error_32:
  321. expect("register");
  322. }
  323. next();
  324. return reg;
  325. }
  326. static void parse_operand(TCCState *s1, Operand *op)
  327. {
  328. ExprValue e;
  329. int reg, indir;
  330. const char *p;
  331. indir = 0;
  332. if (tok == '*') {
  333. next();
  334. indir = OP_INDIR;
  335. }
  336. if (tok == '%') {
  337. next();
  338. if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
  339. reg = tok - TOK_ASM_al;
  340. op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
  341. op->reg = reg & 7;
  342. if ((op->type & OP_REG) && op->reg == TREG_XAX)
  343. op->type |= OP_EAX;
  344. else if (op->type == OP_REG8 && op->reg == TREG_XCX)
  345. op->type |= OP_CL;
  346. else if (op->type == OP_REG16 && op->reg == TREG_XDX)
  347. op->type |= OP_DX;
  348. } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
  349. op->type = OP_DB;
  350. op->reg = tok - TOK_ASM_dr0;
  351. } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
  352. op->type = OP_SEG;
  353. op->reg = tok - TOK_ASM_es;
  354. } else if (tok == TOK_ASM_st) {
  355. op->type = OP_ST;
  356. op->reg = 0;
  357. next();
  358. if (tok == '(') {
  359. next();
  360. if (tok != TOK_PPNUM)
  361. goto reg_error;
  362. p = tokc.str.data;
  363. reg = p[0] - '0';
  364. if ((unsigned)reg >= 8 || p[1] != '\0')
  365. goto reg_error;
  366. op->reg = reg;
  367. next();
  368. skip(')');
  369. }
  370. if (op->reg == 0)
  371. op->type |= OP_ST0;
  372. goto no_skip;
  373. #ifdef TCC_TARGET_X86_64
  374. } else if (tok >= TOK_ASM_spl && tok <= TOK_ASM_dil) {
  375. op->type = OP_REG8 | OP_REG8_LOW;
  376. op->reg = 4 + tok - TOK_ASM_spl;
  377. } else if ((op->reg = asm_parse_numeric_reg(tok, &op->type)) >= 0) {
  378. ;
  379. #endif
  380. } else {
  381. reg_error:
  382. tcc_error("unknown register %%%s", get_tok_str(tok, &tokc));
  383. }
  384. next();
  385. no_skip: ;
  386. } else if (tok == '$') {
  387. /* constant value */
  388. next();
  389. asm_expr(s1, &e);
  390. op->type = OP_IM32;
  391. op->e = e;
  392. if (!op->e.sym) {
  393. if (op->e.v == (uint8_t)op->e.v)
  394. op->type |= OP_IM8;
  395. if (op->e.v == (int8_t)op->e.v)
  396. op->type |= OP_IM8S;
  397. if (op->e.v == (uint16_t)op->e.v)
  398. op->type |= OP_IM16;
  399. #ifdef TCC_TARGET_X86_64
  400. if (op->e.v != (int32_t)op->e.v && op->e.v != (uint32_t)op->e.v)
  401. op->type = OP_IM64;
  402. #endif
  403. }
  404. } else {
  405. /* address(reg,reg2,shift) with all variants */
  406. op->type = OP_EA;
  407. op->reg = -1;
  408. op->reg2 = -1;
  409. op->shift = 0;
  410. if (tok != '(') {
  411. asm_expr(s1, &e);
  412. op->e = e;
  413. } else {
  414. next();
  415. if (tok == '%') {
  416. unget_tok('(');
  417. op->e.v = 0;
  418. op->e.sym = NULL;
  419. } else {
  420. /* bracketed offset expression */
  421. asm_expr(s1, &e);
  422. if (tok != ')')
  423. expect(")");
  424. next();
  425. op->e.v = e.v;
  426. op->e.sym = e.sym;
  427. }
  428. op->e.pcrel = 0;
  429. }
  430. if (tok == '(') {
  431. unsigned int type = 0;
  432. next();
  433. if (tok != ',') {
  434. op->reg = asm_parse_reg(&type);
  435. }
  436. if (tok == ',') {
  437. next();
  438. if (tok != ',') {
  439. op->reg2 = asm_parse_reg(&type);
  440. }
  441. if (tok == ',') {
  442. next();
  443. op->shift = get_reg_shift(s1);
  444. }
  445. }
  446. if (type & OP_REG32)
  447. op->type |= OP_EA32;
  448. skip(')');
  449. }
  450. if (op->reg == -1 && op->reg2 == -1)
  451. op->type |= OP_ADDR;
  452. }
  453. op->type |= indir;
  454. }
  455. /* XXX: unify with C code output ? */
  456. ST_FUNC void gen_expr32(ExprValue *pe)
  457. {
  458. if (pe->pcrel)
  459. /* If PC-relative, always set VT_SYM, even without symbol,
  460. so as to force a relocation to be emitted. */
  461. gen_addrpc32(VT_SYM, pe->sym, pe->v);
  462. else
  463. gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
  464. }
  465. #ifdef TCC_TARGET_X86_64
  466. ST_FUNC void gen_expr64(ExprValue *pe)
  467. {
  468. gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
  469. }
  470. #endif
  471. /* XXX: unify with C code output ? */
  472. static void gen_disp32(ExprValue *pe)
  473. {
  474. Sym *sym = pe->sym;
  475. ElfSym *esym = elfsym(sym);
  476. if (esym && esym->st_shndx == cur_text_section->sh_num) {
  477. /* same section: we can output an absolute value. Note
  478. that the TCC compiler behaves differently here because
  479. it always outputs a relocation to ease (future) code
  480. elimination in the linker */
  481. gen_le32(pe->v + esym->st_value - ind - 4);
  482. } else {
  483. if (sym && sym->type.t == VT_VOID) {
  484. sym->type.t = VT_FUNC;
  485. sym->type.ref = NULL;
  486. }
  487. gen_addrpc32(VT_SYM, sym, pe->v);
  488. }
  489. }
  490. /* generate the modrm operand */
  491. static inline int asm_modrm(int reg, Operand *op)
  492. {
  493. int mod, reg1, reg2, sib_reg1;
  494. if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
  495. g(0xc0 + (reg << 3) + op->reg);
  496. } else if (op->reg == -1 && op->reg2 == -1) {
  497. /* displacement only */
  498. #ifdef TCC_TARGET_X86_64
  499. g(0x04 + (reg << 3));
  500. g(0x25);
  501. #else
  502. g(0x05 + (reg << 3));
  503. #endif
  504. gen_expr32(&op->e);
  505. #ifdef TCC_TARGET_X86_64
  506. } else if (op->reg == -2) {
  507. ExprValue *pe = &op->e;
  508. g(0x05 + (reg << 3));
  509. gen_addrpc32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
  510. return ind;
  511. #endif
  512. } else {
  513. sib_reg1 = op->reg;
  514. /* fist compute displacement encoding */
  515. if (sib_reg1 == -1) {
  516. sib_reg1 = 5;
  517. mod = 0x00;
  518. } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
  519. mod = 0x00;
  520. } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
  521. mod = 0x40;
  522. } else {
  523. mod = 0x80;
  524. }
  525. /* compute if sib byte needed */
  526. reg1 = op->reg;
  527. if (op->reg2 != -1)
  528. reg1 = 4;
  529. g(mod + (reg << 3) + reg1);
  530. if (reg1 == 4) {
  531. /* add sib byte */
  532. reg2 = op->reg2;
  533. if (reg2 == -1)
  534. reg2 = 4; /* indicate no index */
  535. g((op->shift << 6) + (reg2 << 3) + sib_reg1);
  536. }
  537. /* add offset */
  538. if (mod == 0x40) {
  539. g(op->e.v);
  540. } else if (mod == 0x80 || op->reg == -1) {
  541. gen_expr32(&op->e);
  542. }
  543. }
  544. return 0;
  545. }
  546. #ifdef TCC_TARGET_X86_64
  547. #define REX_W 0x48
  548. #define REX_R 0x44
  549. #define REX_X 0x42
  550. #define REX_B 0x41
  551. static void asm_rex(int width64, Operand *ops, int nb_ops, int *op_type,
  552. int regi, int rmi)
  553. {
  554. unsigned char rex = width64 ? 0x48 : 0;
  555. int saw_high_8bit = 0;
  556. int i;
  557. if (rmi == -1) {
  558. /* No mod/rm byte, but we might have a register op nevertheless
  559. (we will add it to the opcode later). */
  560. for(i = 0; i < nb_ops; i++) {
  561. if (op_type[i] & (OP_REG | OP_ST)) {
  562. if (ops[i].reg >= 8) {
  563. rex |= REX_B;
  564. ops[i].reg -= 8;
  565. } else if (ops[i].type & OP_REG8_LOW)
  566. rex |= 0x40;
  567. else if (ops[i].type & OP_REG8 && ops[i].reg >= 4)
  568. /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
  569. saw_high_8bit = ops[i].reg;
  570. break;
  571. }
  572. }
  573. } else {
  574. if (regi != -1) {
  575. if (ops[regi].reg >= 8) {
  576. rex |= REX_R;
  577. ops[regi].reg -= 8;
  578. } else if (ops[regi].type & OP_REG8_LOW)
  579. rex |= 0x40;
  580. else if (ops[regi].type & OP_REG8 && ops[regi].reg >= 4)
  581. /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
  582. saw_high_8bit = ops[regi].reg;
  583. }
  584. if (ops[rmi].type & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_EA)) {
  585. if (ops[rmi].reg >= 8) {
  586. rex |= REX_B;
  587. ops[rmi].reg -= 8;
  588. } else if (ops[rmi].type & OP_REG8_LOW)
  589. rex |= 0x40;
  590. else if (ops[rmi].type & OP_REG8 && ops[rmi].reg >= 4)
  591. /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
  592. saw_high_8bit = ops[rmi].reg;
  593. }
  594. if (ops[rmi].type & OP_EA && ops[rmi].reg2 >= 8) {
  595. rex |= REX_X;
  596. ops[rmi].reg2 -= 8;
  597. }
  598. }
  599. if (rex) {
  600. if (saw_high_8bit)
  601. tcc_error("can't encode register %%%ch when REX prefix is required",
  602. "acdb"[saw_high_8bit-4]);
  603. g(rex);
  604. }
  605. }
  606. #endif
  607. static void maybe_print_stats (void)
  608. {
  609. static int already = 1;
  610. if (!already)
  611. /* print stats about opcodes */
  612. {
  613. const struct ASMInstr *pa;
  614. int freq[4];
  615. int op_vals[500];
  616. int nb_op_vals, i, j;
  617. already = 1;
  618. nb_op_vals = 0;
  619. memset(freq, 0, sizeof(freq));
  620. for(pa = asm_instrs; pa->sym != 0; pa++) {
  621. freq[pa->nb_ops]++;
  622. //for(i=0;i<pa->nb_ops;i++) {
  623. for(j=0;j<nb_op_vals;j++) {
  624. //if (pa->op_type[i] == op_vals[j])
  625. if (pa->instr_type == op_vals[j])
  626. goto found;
  627. }
  628. //op_vals[nb_op_vals++] = pa->op_type[i];
  629. op_vals[nb_op_vals++] = pa->instr_type;
  630. found: ;
  631. //}
  632. }
  633. for(i=0;i<nb_op_vals;i++) {
  634. int v = op_vals[i];
  635. //if ((v & (v - 1)) != 0)
  636. printf("%3d: %08x\n", i, v);
  637. }
  638. printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
  639. (int)sizeof(asm_instrs),
  640. (int)sizeof(asm_instrs) / (int)sizeof(ASMInstr),
  641. freq[0], freq[1], freq[2], freq[3]);
  642. }
  643. }
  644. ST_FUNC void asm_opcode(TCCState *s1, int opcode)
  645. {
  646. const ASMInstr *pa;
  647. int i, modrm_index, modreg_index, reg, v, op1, seg_prefix, pc;
  648. int nb_ops, s;
  649. Operand ops[MAX_OPERANDS], *pop;
  650. int op_type[3]; /* decoded op type */
  651. int alltypes; /* OR of all operand types */
  652. int autosize;
  653. int p66;
  654. #ifdef TCC_TARGET_X86_64
  655. int rex64;
  656. #endif
  657. maybe_print_stats();
  658. /* force synthetic ';' after prefix instruction, so we can handle */
  659. /* one-line things like "rep stosb" instead of only "rep\nstosb" */
  660. if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
  661. unget_tok(';');
  662. /* get operands */
  663. pop = ops;
  664. nb_ops = 0;
  665. seg_prefix = 0;
  666. alltypes = 0;
  667. for(;;) {
  668. if (tok == ';' || tok == TOK_LINEFEED)
  669. break;
  670. if (nb_ops >= MAX_OPERANDS) {
  671. tcc_error("incorrect number of operands");
  672. }
  673. parse_operand(s1, pop);
  674. if (tok == ':') {
  675. if (pop->type != OP_SEG || seg_prefix)
  676. tcc_error("incorrect prefix");
  677. seg_prefix = segment_prefixes[pop->reg];
  678. next();
  679. parse_operand(s1, pop);
  680. if (!(pop->type & OP_EA)) {
  681. tcc_error("segment prefix must be followed by memory reference");
  682. }
  683. }
  684. pop++;
  685. nb_ops++;
  686. if (tok != ',')
  687. break;
  688. next();
  689. }
  690. s = 0; /* avoid warning */
  691. again:
  692. /* optimize matching by using a lookup table (no hashing is needed
  693. !) */
  694. for(pa = asm_instrs; pa->sym != 0; pa++) {
  695. int it = pa->instr_type & OPCT_MASK;
  696. s = 0;
  697. if (it == OPC_FARITH) {
  698. v = opcode - pa->sym;
  699. if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
  700. continue;
  701. } else if (it == OPC_ARITH) {
  702. if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
  703. continue;
  704. s = (opcode - pa->sym) % NBWLX;
  705. if ((pa->instr_type & OPC_BWLX) == OPC_WLX)
  706. {
  707. /* We need to reject the xxxb opcodes that we accepted above.
  708. Note that pa->sym for WLX opcodes is the 'w' token,
  709. to get the 'b' token subtract one. */
  710. if (((opcode - pa->sym + 1) % NBWLX) == 0)
  711. continue;
  712. s++;
  713. }
  714. } else if (it == OPC_SHIFT) {
  715. if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
  716. continue;
  717. s = (opcode - pa->sym) % NBWLX;
  718. } else if (it == OPC_TEST) {
  719. if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
  720. continue;
  721. /* cmovxx is a test opcode but accepts multiple sizes.
  722. The suffixes aren't encoded in the table, instead we
  723. simply force size autodetection always and deal with suffixed
  724. variants below when we don't find e.g. "cmovzl". */
  725. if (pa->instr_type & OPC_WLX)
  726. s = NBWLX - 1;
  727. } else if (pa->instr_type & OPC_B) {
  728. #ifdef TCC_TARGET_X86_64
  729. /* Some instructions don't have the full size but only
  730. bwl form. insb e.g. */
  731. if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
  732. && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
  733. continue;
  734. #endif
  735. if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
  736. continue;
  737. s = opcode - pa->sym;
  738. } else if (pa->instr_type & OPC_WLX) {
  739. if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
  740. continue;
  741. s = opcode - pa->sym + 1;
  742. } else {
  743. if (pa->sym != opcode)
  744. continue;
  745. }
  746. if (pa->nb_ops != nb_ops)
  747. continue;
  748. #ifdef TCC_TARGET_X86_64
  749. /* Special case for moves. Selecting the IM64->REG64 form
  750. should only be done if we really have an >32bit imm64, and that
  751. is hardcoded. Ignore it here. */
  752. if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
  753. && (ops[1].type & OP_REG) == OP_REG64
  754. && !(pa->instr_type & OPC_0F))
  755. continue;
  756. #endif
  757. /* now decode and check each operand */
  758. alltypes = 0;
  759. for(i = 0; i < nb_ops; i++) {
  760. int op1, op2;
  761. op1 = pa->op_type[i];
  762. op2 = op1 & 0x1f;
  763. switch(op2) {
  764. case OPT_IM:
  765. v = OP_IM8 | OP_IM16 | OP_IM32;
  766. break;
  767. case OPT_REG:
  768. v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
  769. break;
  770. case OPT_REGW:
  771. v = OP_REG16 | OP_REG32 | OP_REG64;
  772. break;
  773. case OPT_IMW:
  774. v = OP_IM16 | OP_IM32;
  775. break;
  776. case OPT_MMXSSE:
  777. v = OP_MMX | OP_SSE;
  778. break;
  779. case OPT_DISP:
  780. case OPT_DISP8:
  781. v = OP_ADDR;
  782. break;
  783. default:
  784. v = 1 << op2;
  785. break;
  786. }
  787. if (op1 & OPT_EA)
  788. v |= OP_EA;
  789. op_type[i] = v;
  790. if ((ops[i].type & v) == 0)
  791. goto next;
  792. alltypes |= ops[i].type;
  793. }
  794. /* all is matching ! */
  795. break;
  796. next: ;
  797. }
  798. if (pa->sym == 0) {
  799. if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
  800. int b;
  801. b = op0_codes[opcode - TOK_ASM_first];
  802. if (b & 0xff00)
  803. g(b >> 8);
  804. g(b);
  805. return;
  806. } else if (opcode <= TOK_ASM_alllast) {
  807. tcc_error("bad operand with opcode '%s'",
  808. get_tok_str(opcode, NULL));
  809. } else {
  810. /* Special case for cmovcc, we accept size suffixes but ignore
  811. them, but we don't want them to blow up our tables. */
  812. TokenSym *ts = table_ident[opcode - TOK_IDENT];
  813. if (ts->len >= 6
  814. && strchr("wlq", ts->str[ts->len-1])
  815. && !memcmp(ts->str, "cmov", 4)) {
  816. opcode = tok_alloc(ts->str, ts->len-1)->tok;
  817. goto again;
  818. }
  819. tcc_error("unknown opcode '%s'", ts->str);
  820. }
  821. }
  822. /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
  823. autosize = NBWLX-1;
  824. #ifdef TCC_TARGET_X86_64
  825. /* XXX the autosize should rather be zero, to not have to adjust this
  826. all the time. */
  827. if ((pa->instr_type & OPC_BWLQ) == OPC_B)
  828. autosize = NBWLX-2;
  829. #endif
  830. if (s == autosize) {
  831. /* Check for register operands providing hints about the size.
  832. Start from the end, i.e. destination operands. This matters
  833. only for opcodes accepting different sized registers, lar and lsl
  834. are such opcodes. */
  835. for(i = nb_ops - 1; s == autosize && i >= 0; i--) {
  836. if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
  837. s = reg_to_size[ops[i].type & OP_REG];
  838. }
  839. if (s == autosize) {
  840. if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
  841. (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
  842. s = 2;
  843. else if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
  844. (ops[0].type & OP_EA))
  845. s = NBWLX - 2;
  846. else
  847. tcc_error("cannot infer opcode suffix");
  848. }
  849. }
  850. #ifdef TCC_TARGET_X86_64
  851. /* Generate addr32 prefix if needed */
  852. for(i = 0; i < nb_ops; i++) {
  853. if (ops[i].type & OP_EA32) {
  854. g(0x67);
  855. break;
  856. }
  857. }
  858. #endif
  859. /* generate data16 prefix if needed */
  860. p66 = 0;
  861. if (s == 1)
  862. p66 = 1;
  863. else {
  864. /* accepting mmx+sse in all operands --> needs 0x66 to
  865. switch to sse mode. Accepting only sse in an operand --> is
  866. already SSE insn and needs 0x66/f2/f3 handling. */
  867. for (i = 0; i < nb_ops; i++)
  868. if ((op_type[i] & (OP_MMX | OP_SSE)) == (OP_MMX | OP_SSE)
  869. && ops[i].type & OP_SSE)
  870. p66 = 1;
  871. }
  872. if (p66)
  873. g(0x66);
  874. #ifdef TCC_TARGET_X86_64
  875. rex64 = 0;
  876. if (pa->instr_type & OPC_48)
  877. rex64 = 1;
  878. else if (s == 3 || (alltypes & OP_REG64)) {
  879. /* generate REX prefix */
  880. int default64 = 0;
  881. for(i = 0; i < nb_ops; i++) {
  882. if (op_type[i] == OP_REG64 && pa->opcode != 0xb8) {
  883. /* If only 64bit regs are accepted in one operand
  884. this is a default64 instruction without need for
  885. REX prefixes, except for movabs(0xb8). */
  886. default64 = 1;
  887. break;
  888. }
  889. }
  890. /* XXX find better encoding for the default64 instructions. */
  891. if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
  892. && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
  893. && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
  894. && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
  895. && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
  896. && !default64)
  897. rex64 = 1;
  898. }
  899. #endif
  900. /* now generates the operation */
  901. if (OPCT_IS(pa->instr_type, OPC_FWAIT))
  902. g(0x9b);
  903. if (seg_prefix)
  904. g(seg_prefix);
  905. v = pa->opcode;
  906. if (pa->instr_type & OPC_0F)
  907. v = ((v & ~0xff) << 8) | 0x0f00 | (v & 0xff);
  908. if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
  909. /* kludge for imul $im, %reg */
  910. nb_ops = 3;
  911. ops[2] = ops[1];
  912. op_type[2] = op_type[1];
  913. } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
  914. v--; /* int $3 case */
  915. nb_ops = 0;
  916. } else if ((v == 0x06 || v == 0x07)) {
  917. if (ops[0].reg >= 4) {
  918. /* push/pop %fs or %gs */
  919. v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
  920. } else {
  921. v += ops[0].reg << 3;
  922. }
  923. nb_ops = 0;
  924. } else if (v <= 0x05) {
  925. /* arith case */
  926. v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
  927. } else if ((pa->instr_type & (OPCT_MASK | OPC_MODRM)) == OPC_FARITH) {
  928. /* fpu arith case */
  929. v += ((opcode - pa->sym) / 6) << 3;
  930. }
  931. /* search which operand will be used for modrm */
  932. modrm_index = -1;
  933. modreg_index = -1;
  934. if (pa->instr_type & OPC_MODRM) {
  935. if (!nb_ops) {
  936. /* A modrm opcode without operands is a special case (e.g. mfence).
  937. It has a group and acts as if there's an register operand 0
  938. (ax). */
  939. i = 0;
  940. ops[i].type = OP_REG;
  941. ops[i].reg = 0;
  942. goto modrm_found;
  943. }
  944. /* first look for an ea operand */
  945. for(i = 0;i < nb_ops; i++) {
  946. if (op_type[i] & OP_EA)
  947. goto modrm_found;
  948. }
  949. /* then if not found, a register or indirection (shift instructions) */
  950. for(i = 0;i < nb_ops; i++) {
  951. if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
  952. goto modrm_found;
  953. }
  954. #ifdef ASM_DEBUG
  955. tcc_error("bad op table");
  956. #endif
  957. modrm_found:
  958. modrm_index = i;
  959. /* if a register is used in another operand then it is
  960. used instead of group */
  961. for(i = 0;i < nb_ops; i++) {
  962. int t = op_type[i];
  963. if (i != modrm_index &&
  964. (t & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
  965. modreg_index = i;
  966. break;
  967. }
  968. }
  969. }
  970. #ifdef TCC_TARGET_X86_64
  971. asm_rex (rex64, ops, nb_ops, op_type, modreg_index, modrm_index);
  972. #endif
  973. if (pa->instr_type & OPC_REG) {
  974. /* mov $im, %reg case */
  975. if (v == 0xb0 && s >= 1)
  976. v += 7;
  977. for(i = 0; i < nb_ops; i++) {
  978. if (op_type[i] & (OP_REG | OP_ST)) {
  979. v += ops[i].reg;
  980. break;
  981. }
  982. }
  983. }
  984. if (pa->instr_type & OPC_B)
  985. v += s >= 1;
  986. if (nb_ops == 1 && pa->op_type[0] == OPT_DISP8) {
  987. ElfSym *esym;
  988. int jmp_disp;
  989. /* see if we can really generate the jump with a byte offset */
  990. esym = elfsym(ops[0].e.sym);
  991. if (!esym || esym->st_shndx != cur_text_section->sh_num)
  992. goto no_short_jump;
  993. jmp_disp = ops[0].e.v + esym->st_value - ind - 2 - (v >= 0xff);
  994. if (jmp_disp == (int8_t)jmp_disp) {
  995. /* OK to generate jump */
  996. ops[0].e.sym = 0;
  997. ops[0].e.v = jmp_disp;
  998. op_type[0] = OP_IM8S;
  999. } else {
  1000. no_short_jump:
  1001. /* long jump will be allowed. need to modify the
  1002. opcode slightly */
  1003. if (v == 0xeb) /* jmp */
  1004. v = 0xe9;
  1005. else if (v == 0x70) /* jcc */
  1006. v += 0x0f10;
  1007. else
  1008. tcc_error("invalid displacement");
  1009. }
  1010. }
  1011. if (OPCT_IS(pa->instr_type, OPC_TEST))
  1012. v += test_bits[opcode - pa->sym];
  1013. op1 = v >> 16;
  1014. if (op1)
  1015. g(op1);
  1016. op1 = (v >> 8) & 0xff;
  1017. if (op1)
  1018. g(op1);
  1019. g(v);
  1020. if (OPCT_IS(pa->instr_type, OPC_SHIFT)) {
  1021. reg = (opcode - pa->sym) / NBWLX;
  1022. if (reg == 6)
  1023. reg = 7;
  1024. } else if (OPCT_IS(pa->instr_type, OPC_ARITH)) {
  1025. reg = (opcode - pa->sym) / NBWLX;
  1026. } else if (OPCT_IS(pa->instr_type, OPC_FARITH)) {
  1027. reg = (opcode - pa->sym) / 6;
  1028. } else {
  1029. reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
  1030. }
  1031. pc = 0;
  1032. if (pa->instr_type & OPC_MODRM) {
  1033. /* if a register is used in another operand then it is
  1034. used instead of group */
  1035. if (modreg_index >= 0)
  1036. reg = ops[modreg_index].reg;
  1037. pc = asm_modrm(reg, &ops[modrm_index]);
  1038. }
  1039. /* emit constants */
  1040. #ifndef TCC_TARGET_X86_64
  1041. if (!(pa->instr_type & OPC_0F)
  1042. && (pa->opcode == 0x9a || pa->opcode == 0xea)) {
  1043. /* ljmp or lcall kludge */
  1044. gen_expr32(&ops[1].e);
  1045. if (ops[0].e.sym)
  1046. tcc_error("cannot relocate");
  1047. gen_le16(ops[0].e.v);
  1048. return;
  1049. }
  1050. #endif
  1051. for(i = 0;i < nb_ops; i++) {
  1052. v = op_type[i];
  1053. if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
  1054. /* if multiple sizes are given it means we must look
  1055. at the op size */
  1056. if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
  1057. if (s == 0)
  1058. v = OP_IM8;
  1059. else if (s == 1)
  1060. v = OP_IM16;
  1061. else if (s == 2 || (v & OP_IM64) == 0)
  1062. v = OP_IM32;
  1063. else
  1064. v = OP_IM64;
  1065. }
  1066. if ((v & (OP_IM8 | OP_IM8S | OP_IM16)) && ops[i].e.sym)
  1067. tcc_error("cannot relocate");
  1068. if (v & (OP_IM8 | OP_IM8S)) {
  1069. g(ops[i].e.v);
  1070. } else if (v & OP_IM16) {
  1071. gen_le16(ops[i].e.v);
  1072. #ifdef TCC_TARGET_X86_64
  1073. } else if (v & OP_IM64) {
  1074. gen_expr64(&ops[i].e);
  1075. #endif
  1076. } else if (pa->op_type[i] == OPT_DISP || pa->op_type[i] == OPT_DISP8) {
  1077. gen_disp32(&ops[i].e);
  1078. } else {
  1079. gen_expr32(&ops[i].e);
  1080. }
  1081. }
  1082. }
  1083. /* after immediate operands, adjust pc-relative address */
  1084. if (pc)
  1085. add32le(cur_text_section->data + pc - 4, pc - ind);
  1086. }
  1087. /* return the constraint priority (we allocate first the lowest
  1088. numbered constraints) */
  1089. static inline int constraint_priority(const char *str)
  1090. {
  1091. int priority, c, pr;
  1092. /* we take the lowest priority */
  1093. priority = 0;
  1094. for(;;) {
  1095. c = *str;
  1096. if (c == '\0')
  1097. break;
  1098. str++;
  1099. switch(c) {
  1100. case 'A':
  1101. pr = 0;
  1102. break;
  1103. case 'a':
  1104. case 'b':
  1105. case 'c':
  1106. case 'd':
  1107. case 'S':
  1108. case 'D':
  1109. pr = 1;
  1110. break;
  1111. case 'q':
  1112. pr = 2;
  1113. break;
  1114. case 'r':
  1115. case 'R':
  1116. case 'p':
  1117. pr = 3;
  1118. break;
  1119. case 'N':
  1120. case 'M':
  1121. case 'I':
  1122. case 'e':
  1123. case 'i':
  1124. case 'm':
  1125. case 'g':
  1126. pr = 4;
  1127. break;
  1128. default:
  1129. tcc_error("unknown constraint '%c'", c);
  1130. pr = 0;
  1131. }
  1132. if (pr > priority)
  1133. priority = pr;
  1134. }
  1135. return priority;
  1136. }
  1137. static const char *skip_constraint_modifiers(const char *p)
  1138. {
  1139. while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
  1140. p++;
  1141. return p;
  1142. }
  1143. /* If T (a token) is of the form "%reg" returns the register
  1144. number and type, otherwise return -1. */
  1145. ST_FUNC int asm_parse_regvar (int t)
  1146. {
  1147. const char *s;
  1148. Operand op;
  1149. if (t < TOK_IDENT)
  1150. return -1;
  1151. s = table_ident[t - TOK_IDENT]->str;
  1152. if (s[0] != '%')
  1153. return -1;
  1154. t = tok_alloc(s+1, strlen(s)-1)->tok;
  1155. unget_tok(t);
  1156. unget_tok('%');
  1157. parse_operand(tcc_state, &op);
  1158. /* Accept only integer regs for now. */
  1159. if (op.type & OP_REG)
  1160. return op.reg;
  1161. else
  1162. return -1;
  1163. }
  1164. #define REG_OUT_MASK 0x01
  1165. #define REG_IN_MASK 0x02
  1166. #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
  1167. ST_FUNC void asm_compute_constraints(ASMOperand *operands,
  1168. int nb_operands, int nb_outputs,
  1169. const uint8_t *clobber_regs,
  1170. int *pout_reg)
  1171. {
  1172. ASMOperand *op;
  1173. int sorted_op[MAX_ASM_OPERANDS];
  1174. int i, j, k, p1, p2, tmp, reg, c, reg_mask;
  1175. const char *str;
  1176. uint8_t regs_allocated[NB_ASM_REGS];
  1177. /* init fields */
  1178. for(i=0;i<nb_operands;i++) {
  1179. op = &operands[i];
  1180. op->input_index = -1;
  1181. op->ref_index = -1;
  1182. op->reg = -1;
  1183. op->is_memory = 0;
  1184. op->is_rw = 0;
  1185. }
  1186. /* compute constraint priority and evaluate references to output
  1187. constraints if input constraints */
  1188. for(i=0;i<nb_operands;i++) {
  1189. op = &operands[i];
  1190. str = op->constraint;
  1191. str = skip_constraint_modifiers(str);
  1192. if (isnum(*str) || *str == '[') {
  1193. /* this is a reference to another constraint */
  1194. k = find_constraint(operands, nb_operands, str, NULL);
  1195. if ((unsigned)k >= i || i < nb_outputs)
  1196. tcc_error("invalid reference in constraint %d ('%s')",
  1197. i, str);
  1198. op->ref_index = k;
  1199. if (operands[k].input_index >= 0)
  1200. tcc_error("cannot reference twice the same operand");
  1201. operands[k].input_index = i;
  1202. op->priority = 5;
  1203. } else if ((op->vt->r & VT_VALMASK) == VT_LOCAL
  1204. && op->vt->sym
  1205. && (reg = op->vt->sym->r & VT_VALMASK) < VT_CONST) {
  1206. op->priority = 1;
  1207. op->reg = reg;
  1208. } else {
  1209. op->priority = constraint_priority(str);
  1210. }
  1211. }
  1212. /* sort operands according to their priority */
  1213. for(i=0;i<nb_operands;i++)
  1214. sorted_op[i] = i;
  1215. for(i=0;i<nb_operands - 1;i++) {
  1216. for(j=i+1;j<nb_operands;j++) {
  1217. p1 = operands[sorted_op[i]].priority;
  1218. p2 = operands[sorted_op[j]].priority;
  1219. if (p2 < p1) {
  1220. tmp = sorted_op[i];
  1221. sorted_op[i] = sorted_op[j];
  1222. sorted_op[j] = tmp;
  1223. }
  1224. }
  1225. }
  1226. for(i = 0;i < NB_ASM_REGS; i++) {
  1227. if (clobber_regs[i])
  1228. regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
  1229. else
  1230. regs_allocated[i] = 0;
  1231. }
  1232. /* esp cannot be used */
  1233. regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
  1234. /* ebp cannot be used yet */
  1235. regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
  1236. /* allocate registers and generate corresponding asm moves */
  1237. for(i=0;i<nb_operands;i++) {
  1238. j = sorted_op[i];
  1239. op = &operands[j];
  1240. str = op->constraint;
  1241. /* no need to allocate references */
  1242. if (op->ref_index >= 0)
  1243. continue;
  1244. /* select if register is used for output, input or both */
  1245. if (op->input_index >= 0) {
  1246. reg_mask = REG_IN_MASK | REG_OUT_MASK;
  1247. } else if (j < nb_outputs) {
  1248. reg_mask = REG_OUT_MASK;
  1249. } else {
  1250. reg_mask = REG_IN_MASK;
  1251. }
  1252. if (op->reg >= 0) {
  1253. if (is_reg_allocated(op->reg))
  1254. tcc_error("asm regvar requests register that's taken already");
  1255. reg = op->reg;
  1256. goto reg_found;
  1257. }
  1258. try_next:
  1259. c = *str++;
  1260. switch(c) {
  1261. case '=':
  1262. goto try_next;
  1263. case '+':
  1264. op->is_rw = 1;
  1265. /* FALL THRU */
  1266. case '&':
  1267. if (j >= nb_outputs)
  1268. tcc_error("'%c' modifier can only be applied to outputs", c);
  1269. reg_mask = REG_IN_MASK | REG_OUT_MASK;
  1270. goto try_next;
  1271. case 'A':
  1272. /* allocate both eax and edx */
  1273. if (is_reg_allocated(TREG_XAX) ||
  1274. is_reg_allocated(TREG_XDX))
  1275. goto try_next;
  1276. op->is_llong = 1;
  1277. op->reg = TREG_XAX;
  1278. regs_allocated[TREG_XAX] |= reg_mask;
  1279. regs_allocated[TREG_XDX] |= reg_mask;
  1280. break;
  1281. case 'a':
  1282. reg = TREG_XAX;
  1283. goto alloc_reg;
  1284. case 'b':
  1285. reg = 3;
  1286. goto alloc_reg;
  1287. case 'c':
  1288. reg = TREG_XCX;
  1289. goto alloc_reg;
  1290. case 'd':
  1291. reg = TREG_XDX;
  1292. goto alloc_reg;
  1293. case 'S':
  1294. reg = 6;
  1295. goto alloc_reg;
  1296. case 'D':
  1297. reg = 7;
  1298. alloc_reg:
  1299. if (is_reg_allocated(reg))
  1300. goto try_next;
  1301. goto reg_found;
  1302. case 'q':
  1303. /* eax, ebx, ecx or edx */
  1304. for(reg = 0; reg < 4; reg++) {
  1305. if (!is_reg_allocated(reg))
  1306. goto reg_found;
  1307. }
  1308. goto try_next;
  1309. case 'r':
  1310. case 'R':
  1311. case 'p': /* A general address, for x86(64) any register is acceptable*/
  1312. /* any general register */
  1313. for(reg = 0; reg < 8; reg++) {
  1314. if (!is_reg_allocated(reg))
  1315. goto reg_found;
  1316. }
  1317. goto try_next;
  1318. reg_found:
  1319. /* now we can reload in the register */
  1320. op->is_llong = 0;
  1321. op->reg = reg;
  1322. regs_allocated[reg] |= reg_mask;
  1323. break;
  1324. case 'e':
  1325. case 'i':
  1326. if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
  1327. goto try_next;
  1328. break;
  1329. case 'I':
  1330. case 'N':
  1331. case 'M':
  1332. if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
  1333. goto try_next;
  1334. break;
  1335. case 'm':
  1336. case 'g':
  1337. /* nothing special to do because the operand is already in
  1338. memory, except if the pointer itself is stored in a
  1339. memory variable (VT_LLOCAL case) */
  1340. /* XXX: fix constant case */
  1341. /* if it is a reference to a memory zone, it must lie
  1342. in a register, so we reserve the register in the
  1343. input registers and a load will be generated
  1344. later */
  1345. if (j < nb_outputs || c == 'm') {
  1346. if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
  1347. /* any general register */
  1348. for(reg = 0; reg < 8; reg++) {
  1349. if (!(regs_allocated[reg] & REG_IN_MASK))
  1350. goto reg_found1;
  1351. }
  1352. goto try_next;
  1353. reg_found1:
  1354. /* now we can reload in the register */
  1355. regs_allocated[reg] |= REG_IN_MASK;
  1356. op->reg = reg;
  1357. op->is_memory = 1;
  1358. }
  1359. }
  1360. break;
  1361. default:
  1362. tcc_error("asm constraint %d ('%s') could not be satisfied",
  1363. j, op->constraint);
  1364. break;
  1365. }
  1366. /* if a reference is present for that operand, we assign it too */
  1367. if (op->input_index >= 0) {
  1368. operands[op->input_index].reg = op->reg;
  1369. operands[op->input_index].is_llong = op->is_llong;
  1370. }
  1371. }
  1372. /* compute out_reg. It is used to store outputs registers to memory
  1373. locations references by pointers (VT_LLOCAL case) */
  1374. *pout_reg = -1;
  1375. for(i=0;i<nb_operands;i++) {
  1376. op = &operands[i];
  1377. if (op->reg >= 0 &&
  1378. (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
  1379. !op->is_memory) {
  1380. for(reg = 0; reg < 8; reg++) {
  1381. if (!(regs_allocated[reg] & REG_OUT_MASK))
  1382. goto reg_found2;
  1383. }
  1384. tcc_error("could not find free output register for reloading");
  1385. reg_found2:
  1386. *pout_reg = reg;
  1387. break;
  1388. }
  1389. }
  1390. /* print sorted constraints */
  1391. #ifdef ASM_DEBUG
  1392. for(i=0;i<nb_operands;i++) {
  1393. j = sorted_op[i];
  1394. op = &operands[j];
  1395. printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
  1396. j,
  1397. op->id ? get_tok_str(op->id, NULL) : "",
  1398. op->constraint,
  1399. op->vt->r,
  1400. op->reg);
  1401. }
  1402. if (*pout_reg >= 0)
  1403. printf("out_reg=%d\n", *pout_reg);
  1404. #endif
  1405. }
  1406. ST_FUNC void subst_asm_operand(CString *add_str,
  1407. SValue *sv, int modifier)
  1408. {
  1409. int r, reg, size, val;
  1410. char buf[64];
  1411. r = sv->r;
  1412. if ((r & VT_VALMASK) == VT_CONST) {
  1413. if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n' &&
  1414. modifier != 'P')
  1415. cstr_ccat(add_str, '$');
  1416. if (r & VT_SYM) {
  1417. const char *name = get_tok_str(sv->sym->v, NULL);
  1418. if (sv->sym->v >= SYM_FIRST_ANOM) {
  1419. /* In case of anonymous symbols ("L.42", used
  1420. for static data labels) we can't find them
  1421. in the C symbol table when later looking up
  1422. this name. So enter them now into the asm label
  1423. list when we still know the symbol. */
  1424. get_asm_sym(tok_alloc(name, strlen(name))->tok, sv->sym);
  1425. }
  1426. cstr_cat(add_str, name, -1);
  1427. if ((uint32_t)sv->c.i == 0)
  1428. goto no_offset;
  1429. cstr_ccat(add_str, '+');
  1430. }
  1431. val = sv->c.i;
  1432. if (modifier == 'n')
  1433. val = -val;
  1434. snprintf(buf, sizeof(buf), "%d", (int)sv->c.i);
  1435. cstr_cat(add_str, buf, -1);
  1436. no_offset:;
  1437. #ifdef TCC_TARGET_X86_64
  1438. if (r & VT_LVAL)
  1439. cstr_cat(add_str, "(%rip)", -1);
  1440. #endif
  1441. } else if ((r & VT_VALMASK) == VT_LOCAL) {
  1442. #ifdef TCC_TARGET_X86_64
  1443. snprintf(buf, sizeof(buf), "%d(%%rbp)", (int)sv->c.i);
  1444. #else
  1445. snprintf(buf, sizeof(buf), "%d(%%ebp)", (int)sv->c.i);
  1446. #endif
  1447. cstr_cat(add_str, buf, -1);
  1448. } else if (r & VT_LVAL) {
  1449. reg = r & VT_VALMASK;
  1450. if (reg >= VT_CONST)
  1451. tcc_error("internal compiler error");
  1452. snprintf(buf, sizeof(buf), "(%%%s)",
  1453. #ifdef TCC_TARGET_X86_64
  1454. get_tok_str(TOK_ASM_rax + reg, NULL)
  1455. #else
  1456. get_tok_str(TOK_ASM_eax + reg, NULL)
  1457. #endif
  1458. );
  1459. cstr_cat(add_str, buf, -1);
  1460. } else {
  1461. /* register case */
  1462. reg = r & VT_VALMASK;
  1463. if (reg >= VT_CONST)
  1464. tcc_error("internal compiler error");
  1465. /* choose register operand size */
  1466. if ((sv->type.t & VT_BTYPE) == VT_BYTE ||
  1467. (sv->type.t & VT_BTYPE) == VT_BOOL)
  1468. size = 1;
  1469. else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
  1470. size = 2;
  1471. #ifdef TCC_TARGET_X86_64
  1472. else if ((sv->type.t & VT_BTYPE) == VT_LLONG ||
  1473. (sv->type.t & VT_BTYPE) == VT_PTR)
  1474. size = 8;
  1475. #endif
  1476. else
  1477. size = 4;
  1478. if (size == 1 && reg >= 4)
  1479. size = 4;
  1480. if (modifier == 'b') {
  1481. if (reg >= 4)
  1482. tcc_error("cannot use byte register");
  1483. size = 1;
  1484. } else if (modifier == 'h') {
  1485. if (reg >= 4)
  1486. tcc_error("cannot use byte register");
  1487. size = -1;
  1488. } else if (modifier == 'w') {
  1489. size = 2;
  1490. } else if (modifier == 'k') {
  1491. size = 4;
  1492. #ifdef TCC_TARGET_X86_64
  1493. } else if (modifier == 'q') {
  1494. size = 8;
  1495. #endif
  1496. }
  1497. switch(size) {
  1498. case -1:
  1499. reg = TOK_ASM_ah + reg;
  1500. break;
  1501. case 1:
  1502. reg = TOK_ASM_al + reg;
  1503. break;
  1504. case 2:
  1505. reg = TOK_ASM_ax + reg;
  1506. break;
  1507. default:
  1508. reg = TOK_ASM_eax + reg;
  1509. break;
  1510. #ifdef TCC_TARGET_X86_64
  1511. case 8:
  1512. reg = TOK_ASM_rax + reg;
  1513. break;
  1514. #endif
  1515. }
  1516. snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
  1517. cstr_cat(add_str, buf, -1);
  1518. }
  1519. }
  1520. /* generate prolog and epilog code for asm statement */
  1521. ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
  1522. int nb_outputs, int is_output,
  1523. uint8_t *clobber_regs,
  1524. int out_reg)
  1525. {
  1526. uint8_t regs_allocated[NB_ASM_REGS];
  1527. ASMOperand *op;
  1528. int i, reg;
  1529. /* Strictly speaking %Xbp and %Xsp should be included in the
  1530. call-preserved registers, but currently it doesn't matter. */
  1531. #ifdef TCC_TARGET_X86_64
  1532. #ifdef TCC_TARGET_PE
  1533. static uint8_t reg_saved[] = { 3, 6, 7, 12, 13, 14, 15 };
  1534. #else
  1535. static uint8_t reg_saved[] = { 3, 12, 13, 14, 15 };
  1536. #endif
  1537. #else
  1538. static uint8_t reg_saved[] = { 3, 6, 7 };
  1539. #endif
  1540. /* mark all used registers */
  1541. memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
  1542. for(i = 0; i < nb_operands;i++) {
  1543. op = &operands[i];
  1544. if (op->reg >= 0)
  1545. regs_allocated[op->reg] = 1;
  1546. }
  1547. if (!is_output) {
  1548. /* generate reg save code */
  1549. for(i = 0; i < sizeof(reg_saved)/sizeof(reg_saved[0]); i++) {
  1550. reg = reg_saved[i];
  1551. if (regs_allocated[reg]) {
  1552. if (reg >= 8)
  1553. g(0x41), reg-=8;
  1554. g(0x50 + reg);
  1555. }
  1556. }
  1557. /* generate load code */
  1558. for(i = 0; i < nb_operands; i++) {
  1559. op = &operands[i];
  1560. if (op->reg >= 0) {
  1561. if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
  1562. op->is_memory) {
  1563. /* memory reference case (for both input and
  1564. output cases) */
  1565. SValue sv;
  1566. sv = *op->vt;
  1567. sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
  1568. sv.type.t = VT_PTR;
  1569. load(op->reg, &sv);
  1570. } else if (i >= nb_outputs || op->is_rw) {
  1571. /* load value in register */
  1572. load(op->reg, op->vt);
  1573. if (op->is_llong) {
  1574. SValue sv;
  1575. sv = *op->vt;
  1576. sv.c.i += 4;
  1577. load(TREG_XDX, &sv);
  1578. }
  1579. }
  1580. }
  1581. }
  1582. } else {
  1583. /* generate save code */
  1584. for(i = 0 ; i < nb_outputs; i++) {
  1585. op = &operands[i];
  1586. if (op->reg >= 0) {
  1587. if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
  1588. if (!op->is_memory) {
  1589. SValue sv;
  1590. sv = *op->vt;
  1591. sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
  1592. sv.type.t = VT_PTR;
  1593. load(out_reg, &sv);
  1594. sv = *op->vt;
  1595. sv.r = (sv.r & ~VT_VALMASK) | out_reg;
  1596. store(op->reg, &sv);
  1597. }
  1598. } else {
  1599. store(op->reg, op->vt);
  1600. if (op->is_llong) {
  1601. SValue sv;
  1602. sv = *op->vt;
  1603. sv.c.i += 4;
  1604. store(TREG_XDX, &sv);
  1605. }
  1606. }
  1607. }
  1608. }
  1609. /* generate reg restore code */
  1610. for(i = sizeof(reg_saved)/sizeof(reg_saved[0]) - 1; i >= 0; i--) {
  1611. reg = reg_saved[i];
  1612. if (regs_allocated[reg]) {
  1613. if (reg >= 8)
  1614. g(0x41), reg-=8;
  1615. g(0x58 + reg);
  1616. }
  1617. }
  1618. }
  1619. }
  1620. ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
  1621. {
  1622. int reg;
  1623. TokenSym *ts;
  1624. #ifdef TCC_TARGET_X86_64
  1625. unsigned int type;
  1626. #endif
  1627. if (!strcmp(str, "memory") ||
  1628. !strcmp(str, "cc") ||
  1629. !strcmp(str, "flags"))
  1630. return;
  1631. ts = tok_alloc(str, strlen(str));
  1632. reg = ts->tok;
  1633. if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
  1634. reg -= TOK_ASM_eax;
  1635. } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
  1636. reg -= TOK_ASM_ax;
  1637. #ifdef TCC_TARGET_X86_64
  1638. } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
  1639. reg -= TOK_ASM_rax;
  1640. } else if ((reg = asm_parse_numeric_reg(reg, &type)) >= 0) {
  1641. ;
  1642. #endif
  1643. } else {
  1644. tcc_error("invalid clobber register '%s'", str);
  1645. }
  1646. clobber_regs[reg] = 1;
  1647. }