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@@ -72,6 +72,10 @@ enum {
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OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
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OPT_SEG,
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OPT_ST,
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+#ifdef TCC_TARGET_X86_64
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+ OPT_REG8_LOW, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but
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+ with REX prefix, not used in insn templates */
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+#endif
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OPT_IM8,
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OPT_IM8S,
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OPT_IM16,
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@@ -120,10 +124,12 @@ enum {
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#define OP_INDIR (1 << OPT_INDIR)
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#ifdef TCC_TARGET_X86_64
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# define OP_REG64 (1 << OPT_REG64)
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+# define OP_REG8_LOW (1 << OPT_REG8_LOW)
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# define OP_IM64 (1 << OPT_IM64)
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# define OP_EA32 (OP_EA << 1)
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#else
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# define OP_REG64 0
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+# define OP_REG8_LOW 0
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# define OP_IM64 0
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# define OP_EA32 0
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#endif
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@@ -272,6 +278,39 @@ static inline int get_reg_shift(TCCState *s1)
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return shift;
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}
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+#ifdef TCC_TARGET_X86_64
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+static int asm_parse_high_reg(int *type)
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+{
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+ int reg = -1;
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+ if (tok >= TOK_IDENT && tok < tok_ident) {
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+ const char *s = table_ident[tok - TOK_IDENT]->str;
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+ char c;
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+ if (*s++ != 'r')
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+ return -1;
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+ /* Don't allow leading '0'. */
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+ if ((c = *s++) >= '1' && c <= '9')
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+ reg = c - '0';
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+ else
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+ return -1;
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+ if ((c = *s) >= '0' && c <= '5')
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+ s++, reg = reg * 10 + c - '0';
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+ if (reg > 15)
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+ return -1;
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+ if ((c = *s) == 0)
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+ *type = OP_REG64;
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+ else if (c == 'b' && !s[1])
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+ *type = OP_REG8;
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+ else if (c == 'w' && !s[1])
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+ *type = OP_REG16;
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+ else if (c == 'd' && !s[1])
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+ *type = OP_REG32;
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+ else
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+ return -1;
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+ }
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+ return reg;
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+}
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+#endif
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+
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static int asm_parse_reg(int *type)
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{
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int reg = 0;
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@@ -281,12 +320,17 @@ static int asm_parse_reg(int *type)
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next();
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if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
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reg = tok - TOK_ASM_eax;
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+ *type = OP_REG32;
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#ifdef TCC_TARGET_X86_64
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- *type = OP_EA32;
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} else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
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reg = tok - TOK_ASM_rax;
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+ *type = OP_REG64;
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} else if (tok == TOK_ASM_rip) {
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- reg = 8;
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+ reg = -2; /* Probably should use different escape code. */
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+ *type = OP_REG64;
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+ } else if ((reg = asm_parse_high_reg(type)) >= 0
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+ && (*type == OP_REG32 || *type == OP_REG64)) {
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+ ;
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#endif
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} else {
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error_32:
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@@ -345,6 +389,13 @@ static void parse_operand(TCCState *s1, Operand *op)
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if (op->reg == 0)
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op->type |= OP_ST0;
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goto no_skip;
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+#ifdef TCC_TARGET_X86_64
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+ } else if (tok >= TOK_ASM_spl && tok <= TOK_ASM_dil) {
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+ op->type = OP_REG8 | OP_REG8_LOW;
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+ op->reg = 4 + tok - TOK_ASM_spl;
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+ } else if ((op->reg = asm_parse_high_reg(&op->type)) >= 0) {
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+ ;
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+#endif
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} else {
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reg_error:
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tcc_error("unknown register %%%s", get_tok_str(tok, &tokc));
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@@ -411,7 +462,7 @@ static void parse_operand(TCCState *s1, Operand *op)
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op->shift = get_reg_shift(s1);
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}
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}
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- if (type & OP_EA32)
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+ if (type & OP_REG32)
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op->type |= OP_EA32;
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skip(')');
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}
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@@ -475,7 +526,7 @@ static inline int asm_modrm(int reg, Operand *op)
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#endif
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gen_expr32(&op->e);
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#ifdef TCC_TARGET_X86_64
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- } else if (op->reg == 8) {
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+ } else if (op->reg == -2) {
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ExprValue *pe = &op->e;
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g(0x05 + (reg << 3));
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gen_addrpc32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
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@@ -516,6 +567,69 @@ static inline int asm_modrm(int reg, Operand *op)
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return 0;
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}
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+#ifdef TCC_TARGET_X86_64
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+#define REX_W 0x48
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+#define REX_R 0x44
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+#define REX_X 0x42
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+#define REX_B 0x41
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+
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+static void asm_rex(int width64, Operand *ops, int nb_ops, int *op_type,
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+ int regi, int rmi)
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+{
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+ unsigned char rex = width64 ? 0x48 : 0;
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+ int saw_high_8bit = 0;
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+ int i;
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+ if (rmi == -1) {
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+ /* No mod/rm byte, but we might have a register op nevertheless
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+ (we will add it to the opcode later). */
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+ for(i = 0; i < nb_ops; i++) {
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+ if (op_type[i] & (OP_REG | OP_ST)) {
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+ if (ops[i].reg >= 8) {
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+ rex |= REX_B;
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+ ops[i].reg -= 8;
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+ } else if (ops[i].type & OP_REG8_LOW)
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+ rex |= 0x40;
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+ else if (ops[i].type & OP_REG8 && ops[i].reg >= 4)
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+ /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
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+ saw_high_8bit = ops[i].reg;
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+ break;
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+ }
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+ }
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+ } else {
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+ if (regi != -1) {
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+ if (ops[regi].reg >= 8) {
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+ rex |= REX_R;
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+ ops[regi].reg -= 8;
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+ } else if (ops[regi].type & OP_REG8_LOW)
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+ rex |= 0x40;
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+ else if (ops[regi].type & OP_REG8 && ops[regi].reg >= 4)
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+ /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
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+ saw_high_8bit = ops[regi].reg;
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+ }
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+ if (ops[rmi].type & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_EA)) {
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+ if (ops[rmi].reg >= 8) {
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+ rex |= REX_B;
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+ ops[rmi].reg -= 8;
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+ } else if (ops[rmi].type & OP_REG8_LOW)
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+ rex |= 0x40;
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+ else if (ops[rmi].type & OP_REG8 && ops[rmi].reg >= 4)
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+ /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
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+ saw_high_8bit = ops[rmi].reg;
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+ }
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+ if (ops[rmi].type & OP_EA && ops[rmi].reg2 >= 8) {
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+ rex |= REX_X;
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+ ops[rmi].reg2 -= 8;
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+ }
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+ }
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+ if (rex) {
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+ if (saw_high_8bit)
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+ tcc_error("can't encode register %%%ch when REX prefix is required",
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+ "acdb"[saw_high_8bit-4]);
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+ g(rex);
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+ }
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+}
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+#endif
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+
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static void maybe_print_stats (void)
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{
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static int already = 1;
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@@ -558,13 +672,16 @@ static void maybe_print_stats (void)
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ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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{
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const ASMInstr *pa;
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- int i, modrm_index, reg, v, op1, seg_prefix, pc;
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+ int i, modrm_index, modreg_index, reg, v, op1, seg_prefix, pc;
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int nb_ops, s;
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Operand ops[MAX_OPERANDS], *pop;
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int op_type[3]; /* decoded op type */
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int alltypes; /* OR of all operand types */
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int autosize;
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int p66;
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+#ifdef TCC_TARGET_X86_64
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+ int rex64;
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+#endif
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maybe_print_stats();
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/* force synthetic ';' after prefix instruction, so we can handle */
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@@ -775,6 +892,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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if (p66)
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g(0x66);
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#ifdef TCC_TARGET_X86_64
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+ rex64 = 0;
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if (s == 3 || (alltypes & OP_REG64)) {
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/* generate REX prefix */
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int default64 = 0;
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@@ -794,7 +912,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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&& opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
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&& opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
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&& !default64)
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- g(0x48);
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+ rex64 = 1;
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}
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#endif
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@@ -830,6 +948,50 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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/* fpu arith case */
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v += ((opcode - pa->sym) / 6) << 3;
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}
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+
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+ /* search which operand will be used for modrm */
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+ modrm_index = -1;
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+ modreg_index = -1;
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+ if (pa->instr_type & OPC_MODRM) {
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+ if (!nb_ops) {
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+ /* A modrm opcode without operands is a special case (e.g. mfence).
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+ It has a group and acts as if there's an register operand 0
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+ (ax). */
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+ i = 0;
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+ ops[i].type = OP_REG;
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+ ops[i].reg = 0;
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+ goto modrm_found;
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+ }
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+ /* first look for an ea operand */
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+ for(i = 0;i < nb_ops; i++) {
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+ if (op_type[i] & OP_EA)
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+ goto modrm_found;
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+ }
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+ /* then if not found, a register or indirection (shift instructions) */
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+ for(i = 0;i < nb_ops; i++) {
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+ if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
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+ goto modrm_found;
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+ }
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+#ifdef ASM_DEBUG
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+ tcc_error("bad op table");
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+#endif
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+ modrm_found:
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+ modrm_index = i;
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+ /* if a register is used in another operand then it is
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+ used instead of group */
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+ for(i = 0;i < nb_ops; i++) {
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+ int t = op_type[i];
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+ if (i != modrm_index &&
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+ (t & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
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+ modreg_index = i;
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+ break;
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+ }
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+ }
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+ }
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+#ifdef TCC_TARGET_X86_64
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+ asm_rex (rex64, ops, nb_ops, op_type, modreg_index, modrm_index);
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+#endif
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+
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if (pa->instr_type & OPC_REG) {
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/* mov $im, %reg case */
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if (v == 0xb0 && s >= 1)
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@@ -881,8 +1043,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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g(op1);
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g(v);
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- /* search which operand will used for modrm */
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- modrm_index = 0;
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if (OPCT_IS(pa->instr_type, OPC_SHIFT)) {
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reg = (opcode - pa->sym) / NBWLX;
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if (reg == 6)
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@@ -897,40 +1057,10 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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pc = 0;
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if (pa->instr_type & OPC_MODRM) {
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- if (!nb_ops) {
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- /* A modrm opcode without operands is a special case (e.g. mfence).
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- It has a group and acts as if there's an register operand 0
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- (ax). */
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- i = 0;
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- ops[i].type = OP_REG;
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- ops[i].reg = 0;
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- goto modrm_found;
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- }
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- /* first look for an ea operand */
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- for(i = 0;i < nb_ops; i++) {
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- if (op_type[i] & OP_EA)
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- goto modrm_found;
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- }
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- /* then if not found, a register or indirection (shift instructions) */
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- for(i = 0;i < nb_ops; i++) {
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- if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
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- goto modrm_found;
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- }
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-#ifdef ASM_DEBUG
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- tcc_error("bad op table");
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-#endif
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- modrm_found:
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- modrm_index = i;
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/* if a register is used in another operand then it is
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used instead of group */
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- for(i = 0;i < nb_ops; i++) {
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- v = op_type[i];
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- if (i != modrm_index &&
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- (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
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- reg = ops[i].reg;
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- break;
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- }
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- }
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+ if (modreg_index >= 0)
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+ reg = ops[modreg_index].reg;
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pc = asm_modrm(reg, &ops[modrm_index]);
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}
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